In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 250ps 350ps 150ps 300ps 200ps Also, assume that instructions executed by the processor are broken down as follows: alu beq sw sw 45% 20% 20% 15% What is the clock cycle time in a pipelined and non-pipelined processor?
